1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more specifically, it relates to a semiconductor device comprising trench isolation insulator films and a method of fabricating the same.
2. Description of the Prior Art
Following refinement and high integration of a semiconductor device, trench isolation oxide films are generally employed for electrically isolating elements which are formed on a major surface of a semiconductor substrate from each other. FIG. 26 is a sectional view for illustrating conventional trench isolation oxide films. With reference to FIG. 26, the conventional trench isolation oxide films are now described.
Referring to FIG. 26, trenches 104a to 104c are formed on a major surface of a semiconductor substrate 101. Thermal oxide films 105a to 105c are formed on surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c respectively. Oxide films 113a to 113c serving as isolation insulator films are formed in the trenches 104a to 104c by chemical vapor deposition (hereinafter referred to as CVD) respectively. The widths W1 of the oxide films 113a to 113c and the intervals therebetween (the widths of element forming regions on the major surface of the semiconductor substrate 101) are set at various values in a single semiconductor device.
FIGS. 27 to 30 are sectional views for illustrating steps of forming the conventional trench isolation oxide films 113a to 113c shown in FIG. 26. With reference to FIGS. 27 to 30, the steps of forming the conventional trench isolation oxide films 113a to 113c are now described.
First, a thermal oxide film (not shown) is formed on the major surface of the semiconductor substrate 101 (see FIG. 27). A silicon nitride film (not shown) is formed on this thermal oxide film. A resist pattern (not shown) is formed on this silicon nitride film and thereafter employed as a mask for partially removing the silicon nitride film and the thermal oxide film by anisotropic etching. Thereafter the resist pattern is removed. Thus, thermal oxide films 102a to 102d and silicon nitride films 103a to 103d are formed on the major surface of the semiconductor substrate 101, as shown in FIG. 27.
Then, the silicon nitride films 103a to 103d are employed as masks for partially removing the semiconductor substrate 101 by anisotropic etching, thereby forming the trenches 104a to 104c as shown in FIG. 28. These trenches 104a to 104c are set at a depth capable of electrically isolating elements in the element forming regions from each other. For example, it is inferred that the depth of such trenches is not more than about 0.35 .mu.m in a DRAM (dynamic random access memory) having a storage capacity of at least 1 gigabyte (G).
After formation of the trenches 104a to 104c, the surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c may have defects resulting from the aforementioned anisotropic etching. In order to remove such defects, the surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c may be thermally oxidized and thereafter partially removed with an HF solution. Alternatively, the surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c may be removed by isotropic etching, or the semiconductor substrate 101 may be heat-treated, in order to remove the aforementioned defects.
Then, the surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c are thermally oxidized, thereby forming the thermal oxide films 105a to 105c, as shown in FIG. 29. Then, an oxide film 113 is deposited on the silicon nitride films 103a to 103d and in the trenches 104a to 104c by CVD.
Then, the oxide film 113 is partially removed by anisotropic etching, thereby obtaining a structure shown in FIG. 30.
Then, the silicon nitride films 103a to 103d and the thermal oxide films 102a to 102d are removed from the major surface of the semiconductor substrate 101 by etching, thereby obtaining the structure shown in FIG. 26. The conventional trench isolation oxide films 113a to 113c are formed in this method.
Higher integration and refinement are increasingly required to semiconductor devices in recent years, particularly in semiconductor memory devices such as DRAMs. Therefore, the widths W1 of the trench isolation oxide films 113a, 113b and 113c shown in FIG. 26 must be further reduced. For example, it is predicted that the widths W1 of such trench isolation oxide films 113a, 113b and 113c are about 0.1 to 0.2 .mu.m in a 1-gigabyte DRAM.
When the widths W1 of the trench isolation oxide films 113a, 113b and 113c are reduced, however, a part of the oxide film 113 formed in the trench 104c and on the silicon nitride films 103c and 103d by CVD may come into contact with an upper portion of the trench 104c to close its opening and define a void 114 in the trench 104c before filling up the same, as shown in FIG. 31. Such a void 114 formed in the trench isolation oxide film 104c deteriorates the isolation property thereof, leading to insufficient electric isolation between the elements formed on the surface of the semiconductor substrate 101. This results in a problem such as a malfunction of the semiconductor device.
In order to fill up narrow trenches with an oxide film while forming no void, proposed is a method of forming trench isolation oxide films through deposition such as HDP-CVD (high density plasma CVD) simultaneously progressing deposition and etching of an oxide film. FIG. 32 is a sectional view showing trench isolation oxide films formed by HDP-CVD. Referring to FIG. 32, trenches 124a to 124c are formed on a major surface of a semiconductor substrate 101. Thermal oxide films 105a to 105c are formed on surface portions of the semiconductor substrate 101 located in the trenches 124a to 124c respectively. Silicon oxide films 115a to 115c are formed by HDP-CVD, to fill up the trenches 124a to 124c respectively. The width W2 of the trenches 124a to 124c is set at 0.25 .mu.m, and the interval W3 between the trenches 124a to 124c is set at 0.55 .mu.m.
FIG. 33 is a sectional view for illustrating a method of forming the trench isolation oxide films shown in FIG. 32 by HDP-CVD. With reference to FIG. 33, the method of forming the trench isolation oxide films by HDP-CVD is now described.
First, thermal oxide films 102a to 102d (see FIG. 33) and silicon nitride films 103a to 103d (see FIG. 33) are formed on the major surface of the semiconductor substrate 101 (see FIG. 33), and the trenches 124a to 124c are formed on the semiconductor substrate 101, through steps similar to those shown in FIGS. 27 and 28.
Then, the thermal oxide films 105a to 105c (see FIG. 33) are formed on the surface portions of the semiconductor substrate 101 located in the trenches 124a to 124c respectively. Then, a silicon oxide film 115 is formed in the trenches 124a to 124c and on the silicon nitride films 103a to 103d by HDP-CVD, as shown in FIG. 33.
At this time, the silicon oxide film 115 is deposited in the trenches 124a to 124c and simultaneously partially sputter-etched on upper portions of the trenches 124a to 124c. Therefore, the parts of the silicon oxide film 115 do not come into contact with the upper portions of the trenches 124a to 124c to close the openings thereof, dissimilarly to the general step of forming the silicon oxide film by the CVD. Parts of the silicon oxide film 115 deposited on the silicon nitride films 103a to 103d are formed to have side surfaces inclined at an angle of about 45.degree., since corner portions of the silicon oxide film 115 are sputter-etched on the upper portions of the trenches 124a to 124c.
Thereafter the parts of the silicon oxide film 115 located on the silicon nitride films 103a to 103d are removed and the silicon nitride films 103a to 103d and the thermal oxide films 102a to 102d are removed from the semiconductor substrate 101 through a step similar to that shown in FIG. 30, thereby obtaining the structure shown in FIG. 32.
Thus, trench isolation oxide films having a narrower width can be formed by HDP-CVD. However, the inventors have further studied and carried out steps of forming a plurality of trench isolation oxide films having different widths and separating from each other at different intervals under conditions closer to those for actual steps of fabricating a semiconductor device, to find out the following subject:
FIGS. 34 to 36 are sectional views for illustrating the steps of forming trench isolation oxide films carried out by the inventors. The steps of forming trench isolation oxide films carried out by the inventors are now described with reference to FIGS. 34 to 36.
First, thermal oxide films 102a to 102d and silicon nitride films 103a to 103d are formed on a major surface of a semiconductor substrate 101 as shown in FIG. 28, through steps similar to those for forming the conventional trench isolation oxide films shown in FIGS. 27 and 28. The silicon nitride films 103a to 103d are employed as masks for partially removing the semiconductor substrate 101 by anisotropic etching, thereby forming trenches 104a to 104c. The widths W6 and W7 (see FIG. 34) of the trenches 104b and 104a are set at 0.2 .mu.m and 2.5 .mu.m respectively.
Then, surface portions of the semiconductor substrate 101 located in the trenches 104a to 104c are thermally oxidized, thereby forming thermal oxide films 105a to 105c (see FIG. 34) respectively. Then, a silicon oxide film 115 (see FIG. 34) is deposited in the trenches 104a to 104c and on the silicon nitride films 103a to 103d by HDP-CVD, thereby obtaining the structure shown in FIG. 34.
As hereinabove described, HDP-CVD is adapted to simultaneously progress deposition and removal of the silicon oxide film 115. In this HDP-CVD, the parts of the silicon oxide film 115 removed by sputter etching are deposited on other regions again, to form the silicon oxide film 115. In this HDP-CVD, the balance between the rates for depositing the oxide film 115 and removing the same by sputter etching can be changed by adjusting the type of gas or the pressure of the atmosphere.
Referring to FIG. 34, consider the case of depositing the silicon oxide film 115 in the trenches 104a and 104b having the different widths W7 and W6 respectively. The portion of the silicon oxide film 115 deposited on an upper portion of a side wall of the trench 104b having the relatively narrow width W6, i.e., a corner portion 119 of the silicon nitride film 103c, is partially removed by sputter etching in HDP-CVD. The part of the silicon oxide film 115 removed by sputter etching is deposited in the vicinity of a corner portion 120 of the opposite silicon nitride film 103b again.
On the other hand, a part of the silicon oxide film 115 similarly removed by sputter etching from an upper portion of a side wall of the trench 104a having the large width W7 may be deposited on an upper portion of an opposite side wall of the trench 104a, while the amount of this deposition is smaller than that in the trench 104b, due to the large width W7 of the trench 104a. Therefore, the conditions for HDP-CVD for filling up the trench 104b having the narrow width W6 must be adjusted to increase the rate for partially removing the silicon oxide film 115 by sputter etching as compared with that for filling up the trench 104a having the large width W7, in order to prevent the silicon oxide film 115 from closing the opening in the upper portion of the trench 104b.
Consequently, the silicon oxide film 115 can fill up the trench 104b having the relatively narrow width W6 while forming no void. However, the oxide film 115 is excessively removed from the upper portion of the side wall of the trench 104a having the large width W6 by sputter etching. Thus, not only parts of the silicon nitride films 103a and 103b and the thermal oxide films 102a and 102b employed as masks but a part of the semiconductor substrate 101 is finally removed from the upper portion of the side wall of the trench 104a by sputter etching, as shown in FIG. 34.
Then, portions of the silicon oxide film 115 located on the silicon nitride films 103a to 103d are removed by etching or chemical mechanical polishing (CMP), as shown in FIG. 35.
Then, the silicon nitride films 103a to 103d and the thermal oxide films 102a to 102d are removed from the semiconductor substrate 101 by etching, thereby obtaining a structure shown in FIG. 36. In the step of depositing the silicon oxide film 115 by HDP-CVD shown in FIG. 34, the silicon nitride films 103a and 103b and the thermal oxide films 102a and 102b employed as masks and the semiconductor substrate 101 are partially removed from the trench 104a having the large width W7. Therefore, a trench isolation oxide film 115a has overhang portions 116a and 116b, as shown in FIG. 36. Consequently, the interval W4 between this isolation oxide film 115a and an isolation oxide film 115b on the major surface of the semiconductor substrate 101 is smaller than the interval W5 therebetween under the major surface of the semiconductor substrate 101.
Due to such overhang portions 116a and 116b of the isolation oxide film 115a, the thickness of a polysilicon film deposited for forming a wire 117 of polysilicon on the isolation oxide film 115a may be irregular in a portion 118 close to the overhang portion 116b, as shown in FIG. 37. In a photolithographic step for forming the wire 117, further, the wire 117 cannot attain a designed shape but may be disconnected or shorted due to the presence of the overhang portions 116a and 116b. Thus, the semiconductor device is disadvantageously reduced in reliability. Further, such a defect results in reduction of the yield of the semiconductor device.
When the silicon oxide film 115 is deposited by HD-CVD, the semiconductor substrate 101 is also partially removed from the upper portion of the side wall of the trench 104a by sputter etching, as shown in FIG. 34. Thus, the semiconductor substrate 101 causes a defect due to such partial removal by sputter etching, to disadvantageously increase leakage currents from element forming regions. Such increase of the leakage currents causes deterioration of the electric characteristics of the semiconductor device, to result in reduction of the reliability of the semiconductor device.